The present invention relates in general to binary amplifiers and to integrated circuits incorporating such binary amplifiers. More particularly, the present invention concerns binary amplifiers integrated in a semi-conductor material and essentially composed of at least one field effect transistor connected to bipolar transistors. Even more particularly, the present invention relates to integrated circuits including field effect transistors of the complementary type and bipolar transistors, such as BiCMOS integrated circuits in which the field transistors are of the CMOS (complementary metal oxide semi-conductor) type. The invention applies notably to binary amplifiers in information processing systems, such as interface amplifiers (buffer amplifiers) connected to output terminals of an integrated circuit to transmit a binary signal to a load circuit. For example, the load circuit may be a bus or an interface with an integrated memory. In applications where several binary amplifiers are connected to a bus, a third logic state, referred to as a high impedance state and controlled by a validation signal, is added to each amplifier. In this state, the binary amplifier assures electrical isolation with the bus in a way so as not to interfere with the signals sent on the bus originating from another amplifier. The invention also concerns these amplifiers.
Integrated binary amplifiers, composed of a field effect transistor as an input element and a bipolar transistor as an output element, have the disadvantage of having a performance that is degraded when the capacitance of the load circuit exceeds a relatively low value of, for example, 10 pF. One solution consists of connecting to the field effect transistor two bipolar transistors in series (Darlington pair). To optimize the time of signal propagation in the amplifier, the electrical charges which accumulate at the bases of the bipolar transistors are eliminated. This elimination is done during the period of blockage of the bipolar transistors, by means of the discharge elements connecting the respective bases of the transistors to a supply potential, usually ground. Each discharge element is a resistance serving for polarization of the bipolar transistors during their functioning, or a field effect transistor in an amplifier not utilizing the resistance. Such an amplifier has the advantage of tolerating large capacitances from its load circuit, up to 200 pF for example, and not necessitating the use of other than standard size transistors.
Most generally, the same advantages are obtained applying the same solution to classic binary amplifiers composed of at least two field effect transistors connected respectively to a bipolar transistor. The most simple of these amplifiers includes two field effect transistors of complementary type receiving the same input signal. The field effect transistor for high level amplification is connected to two bipolar transistors in series. The field effect transistor for low level amplification is connected to a single bipolar transistor. In the amplifier, the base of each bipolar transistor is provided with an element for discharge of capacitance, which may be a resistor or a field effect transistor. Such an amplifier is described in U.S. Pat. No. 4,638,186. However, putting bipolar transistors in series has the disadvantage cf reducing the excursion of the output signal. This disadvantage clearly appears when using, for example, an amplifier composed of a pair of CMOS transistors each connected to two bipolar transistors in series. It is known that the voltage of the emitter-base junction (Vbe) of a bipolar transistor may attain 0.8 volts. As a consequence, if for example, the supply potentials are ground and +5 volts, the output signal oscillates between approximately 1.6 volts and 3.4 volts. In other words, the amplitude of the output signal is only around 2.6 volts, which would be approximately the average of the supply voltage (5 volts). The first consequence of a reduced amplitude is that the output signal is very sensitive to noise. A parasitic signal can alter the function of the component controlled by the amplifier. As a second consequence, the output signal may no longer be compatible with a load circuit including an integrated circuit--an integrated memory for example--made with TTL (transistor-transistor logic) technology. This technology requires potentials that may not be attained by a too much weakened binary amplifier output signal. The third consequence resides in the necessity of having an elevated supply voltage. This requirement is contrary to the current tendency to utilize weaker supply voltages, 3 volts for example. It is also clear, as a fourth consequence, that it is impossible to connect three binary transistors in series to accommodate an amplifier with a load circuit that is very strongly capacitive, over 200 pF for example. Another very important consequence is the fact that the low level of the output signal differs from the reference potential, usually ground, of the voltage of junction Vbe of each bipolar transistor utilized for low level amplification. The Vbe voltage gemerates, in numerous applications, a parasitic current in the load circuit of the amplifier. For example, if the load circuit is an integrated memory, composed of several cells, a leakage current across the transistors of each cell occurs, such that the total of these leakage currents in the cells produce relatively elevated differences in potential which can disturb the desired operation of the memory. To limit the low level of the output signal to a single Vbe voltage to ground, the low level amplification is ordinarily made by only one bipolar transistor whereas the high level amplification is made by a Darlington circuit, as illustrated in U.S. Pat. No. 4,638,186 mentioned above. This then essentially limits the desired performance of the amplifier.
In U.S. Pat. No. 4,476,403, the output circuit of the amplifier also contains a bipolar transistor for low level amplification and two transistors in series constituting a Darlington pair for high level amplification. The low level bipolar transistor is of the Schottky type in order to present a Vbe voltage of about 0.3 volts. In the Darlington pair serving for high-level amplification, the Vbe voltage of the first transistor is substantially shunted by a connection applying the base of the output bipolar transistor to a fixed potential. However, the structure and operation of the shunt connection which is described and illustrated in this patent is complex, difficult to execute and only applicable to TTL technology.